Renesas Electronics /R7FA4E10D /AGT0 /AGTMR1

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Interpret as AGTMR1

7 43 0 0 00 0 0 0 0 0 0 0 0 (Others)TMOD0 (0)TEDGPL 0 (Others)TCK

TEDGPL=0, TMOD=Others, TCK=Others

Description

AGT Mode Register 1

Fields

TMOD

Operating Mode

0 (000): Timer mode

0 (Others): Setting prohibited

1 (001): Pulse output mode

2 (010): Event counter mode

3 (011): Pulse width measurement mode

4 (100): Pulse period measurement mode

TEDGPL

Edge Polarity

0 (0): Single-edge

1 (1): Both-edge

TCK

Count Source

0 (000): PCLKB

0 (Others): Setting prohibited

1 (001): PCLKB/8

3 (011): PCLKB/2

4 (100): Divided clock AGTLCLK specified by CKS[2:0] bits in the AGTMR2 register

5 (101): Underflow event signal from AGTn (n = 0, 2)

6 (110): Divided clock AGTSCLK specified by CKS[2:0] bits in the AGTMR2 register

Links

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